Job ID: JOB_ID_3479
Job Overview:
We are seeking a highly skilled SerDes Design Engineer to join the high-speed I/O design team working on next-generation semiconductor products. The ideal candidate will have strong expertise in SerDes PHY design, analog and mixed-signal circuit design, and high-speed communication interfaces. The role involves designing and developing high-speed serial interfaces and collaborating with cross-functional teams including digital design, layout, and validation teams.
Key Responsibilities:
- Design and develop high-speed SerDes PHY architectures including Transmitter (TX), Receiver (RX), PLL, and Clock/Data Recovery (CDR) circuits.
- Implement and optimize equalization techniques such as CTLE, DFE, and FFE.
- Perform circuit design, simulation, and verification in deep submicron CMOS technologies.
- Conduct pre-layout and post-layout simulations to ensure performance across PVT corners.
- Analyze signal integrity including jitter analysis, channel modeling, and eye diagram analysis.
- Collaborate with digital, layout, and validation teams for design integration.
- Support system-level integration and silicon bring-up activities.
- Participate in design reviews and technical discussions to improve architecture and performance.
- Troubleshoot silicon issues and contribute to performance optimization.
Required Qualifications:
- Bachelors or Masters degree in Electrical Engineering or related field.
- 5+ years (Mid-Level) or 8+ years (Senior) of experience in SerDes / High-Speed IO design.
- Strong knowledge of analog and mixed-signal circuit design.
- Experience with high-speed communication protocols such as PCIe, Ethernet, USB, SATA, or DisplayPort.
- Hands-on experience with EDA tools such as Cadence or Synopsys.
- Solid understanding of signal integrity concepts and high-speed communication theory.
Preferred Qualifications:
- Experience working with advanced semiconductor process nodes such as 7nm, 5nm, or 3nm.
- Silicon validation and lab bring-up experience.
- Scripting experience with Python or MATLAB for modeling and analysis.
- Prior experience delivering production-quality SerDes IP.
Special Requirements
Visa constraints: None specified. Screening steps: None specified. Interview modes: Not specified. Domain restrictions: None specified.
Compensation & Location
Salary: $70 – $100 per year (Estimated)
Location: San Francisco, CA
Recruiter / Company – Contact Information
Email: h@infowaygroup.com
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