Job ID: JOB_ID_399
Role Overview
We are seeking a highly experienced FPGA Verification Engineer for a long-term, onsite engagement with one of our Fortune 100 clients in Mountain View, California. This role requires a deep technical understanding of FPGA design principles and a mastery of modern verification methodologies. As a senior member of the hardware engineering team, you will be responsible for ensuring the functional correctness of complex FPGA designs that power next-generation computing platforms. The ideal candidate will possess a rigorous approach to verification, ensuring that every gate and signal path is validated against the highest industry standards.
Key Responsibilities
- Develop and implement comprehensive verification plans for complex FPGA designs using System Verilog and UVM.
- Architect and maintain scalable UVM-based testbenches, including drivers, monitors, scoreboards, and sequencers.
- Perform RTL and gate-level simulations using industry-standard tools such as QuestaSim and Synopsys VCS.
- Define and track functional coverage metrics to ensure all design features and corner cases are thoroughly verified.
- Analyze code coverage reports to identify and close gaps in the verification suite.
- Collaborate closely with RTL designers to debug complex hardware issues and provide feedback on design-for-verification (DFV) strategies.
- Utilize scripting languages like Python or Perl to automate verification workflows and regression testing.
- Document verification environments, test plans, and results to maintain high standards of engineering rigor.
- Participate in design reviews and provide critical feedback on hardware architecture from a verification perspective.
- Stay abreast of emerging verification technologies and methodologies to continuously improve the team’s efficiency.
Required Technical Skills
- Minimum of 8 years of professional experience in FPGA design and verification.
- At least 5 years of hands-on experience with Universal Verification Methodology (UVM).
- Expert-level proficiency in System Verilog for hardware verification.
- Strong background in hardware description languages, including VHDL and Verilog.
- Proven track record of debugging complex SOC/FPGA systems at the waveform level.
- Experience with high-speed interfaces and memory controllers is highly desirable.
- Familiarity with Agile hardware development processes and version control systems like Git.
- Knowledge of formal verification techniques is a significant plus.
Education and Professional Background
- Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a closely related field.
- Excellent communication skills with the ability to articulate technical challenges to cross-functional teams.
- Strong problem-solving mindset and the ability to work independently in a fast-paced environment.
- Ability to work onsite 5 days a week in Mountain View, CA.
Special Requirements
Visa constraints: No GC/USC/GCEAD (H1B/C2C preferred); Location: Local to California needed; Work Mode: 05 days onsite.
Compensation & Location
Salary: $160,000 – $220,000 per year (Estimated)
Location: Mountain View, CA
Recruiter / Company – Contact Information
Recruiter / Employer: Buckeye Global IT Inc.
Email: amar@buckeyeglobalit.com
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