Job ID: 3181806
Overview of the Lead SoC/Sub-System Design Verification Role
Adventa Tech is actively seeking a highly experienced and dynamic Lead SoC/Sub-System Design Verification Engineer to join our innovative team in Sunnyvale, CA. This critical onsite contract position, spanning six months, is designed for a seasoned professional with over 12 years of dedicated experience in SoC design and verification. The successful candidate will be instrumental in driving our SoC-level verification strategy, leading high-performing teams, and ultimately ensuring the delivery of first-time-right silicon. This role demands not only deep technical expertise but also exceptional leadership qualities and the ability to effectively influence cross-functional teams within a fast-paced and challenging environment. We are looking for a visionary leader who can navigate complex technical challenges and foster a culture of excellence and continuous improvement.
Key Responsibilities and Impact Areas
- Strategic Verification Leadership: Lead a dedicated SoC Verification team, taking full ownership of the comprehensive verification of the SoC and the seamless integration of its various subsystems and associated flows. This includes defining, driving, and executing robust verification strategies, encompassing detailed test plans, clear requirements, sophisticated verification environments, advanced tools, and cutting-edge methodologies.
- Architectural Collaboration and Review: Proactively review intricate architecture specifications and collaborate closely with architects and RTL designers. Your expertise will be crucial in assessing the potential impacts of architectural changes on verification efforts and ensuring alignment with overall project goals.
- Advanced Testbench Development: Design, develop, and meticulously maintain UVM/SystemVerilog-based testbenches. These testbenches will be utilized for rigorous block, subsystem/cluster, and full-chip verification, ensuring thorough coverage and defect detection.
- Comprehensive Verification Execution: Drive the implementation of functional coverage models, develop effective simulation strategies, formulate detailed emulation plans, and strategically utilize formal verification techniques where applicable to maximize verification efficiency and effectiveness.
- Gate-Level Simulation and Signoff: Perform and expertly guide Gate-Level Simulation (GLS) bring-up, conduct precise timing simulations, and manage all critical signoff activities to ensure design integrity and readiness for tape-out.
- Complex Debugging and Problem Solving: Debug complex SoC level issues across various environments, including simulation, emulation, and silicon-like setups, demonstrating strong analytical and problem-solving capabilities.
- Mentorship and Team Development: Actively mentor and coach team members, fostering their technical growth, promoting knowledge sharing, and cultivating a culture of technical excellence within the team.
- Cross-Functional Collaboration: Collaborate effectively with diverse cross-functional stakeholders, including design, architecture, and software teams, to deliver robust SoC verification solutions and ensure on-schedule, high-quality deliverables that meet stringent project requirements.
Essential Qualifications and Technical Acumen
- Extensive Experience: A minimum of 12 years of hands-on experience in the field of SoC design and verification is absolutely essential.
- Verification Expertise: Demonstrated strong expertise in Universal Verification Methodology (UVM), Unified Power Format (UPF), and various protocol VIPs (Verification Intellectual Property).
- Strategic Verification Acumen: Proven ability to define, implement, and successfully execute complex verification strategies at both the SoC and subsystem levels.
- Protocol Knowledge: Hands-on experience with industry-standard AMBA protocols (AXI, AHB, APB) and practical experience with at least one high-speed or memory protocol.
- Programming and Scripting Proficiency: Proficient in SystemVerilog, VHDL, Python, and TCL scripting languages, enabling efficient testbench development and automation.
- Deep Methodological Understanding: A deep and comprehensive understanding of functional coverage, constrained random verification, advanced simulation techniques, emulation platforms, and formal verification methods.
- Architectural Engagement: Experience participating in or actively driving architecture reviews and adeptness at reacting to dynamic design and architecture changes.
- Debugging Prowess: Exceptional debugging skills coupled with the ability to work independently and effectively in demanding, fast-paced environments.
- Leadership and Influence: Demonstrated ability to lead technical teams, influence key stakeholders, and consistently deliver strategic technical solutions that align with business objectives.
- Educational Background: A Master’s degree in Electrical Engineering, Computer Science, or a closely related technical field is required.
Desirable Skills and Attributes
- Experience with performance verification methodologies and tools.
- Hands-on exposure to formal verification methodologies and their practical application.
This role offers a unique opportunity to contribute to cutting-edge silicon development and lead a talented team in a highly innovative environment. If you are a driven and experienced verification leader looking for your next challenge, we encourage you to apply.
Special Requirements
Interview Mode: Skype. Must have LinkedIn profile.
Compensation & Location
Salary: $180,000 – $250,000 per year (Estimated)
Location: Sunnyvale, CA
Recruiter / Company – Contact Information
Recruiter / Employer: Adventa Tech
Email: subhasri@adventatech.com
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