Job ID: JOB_ID_1284
Position Summary
Adventa Tech is currently seeking a Senior Silicon Design Verification Engineer for a high-profile role in Santa Clara, California. This position is open to candidates seeking Contract, Contract-to-Hire, or Full-Time/Permanent opportunities. We are looking for a highly technical individual with 7 to 17 years of experience in the semiconductor industry, specifically focused on advanced verification methodologies. This is an onsite role requiring local presence in the Santa Clara area.
Core Responsibilities
- Perform hands-on design verification at both the IP and subsystem levels for complex silicon designs.
- Develop and maintain comprehensive UVM (Universal Verification Methodology) testbenches using System Verilog.
- Author detailed verification plans and implement sequences, scoreboards, and functional coverage.
- Execute verification and debugging for a variety of industry-standard protocols, including PCIe, Ethernet, USB, DDR, I2C, SPI, and UART.
- Integrate and debug third-party Verification Intellectual Property (VIP) from major vendors such as Synopsys and Cadence.
- Conduct gate-level simulations (GLS) and power-aware verification using X-propagation (X-prop) and Unified Power Format (UPF).
- Utilize advanced debugging tools, including waveform viewers and log analysis, to identify and resolve hardware bugs.
- Collaborate closely with RTL design and silicon architecture teams to ensure design specifications are met.
- Support the verification sign-off process through rigorous documentation and coverage analysis.
Technical Requirements
- 7+ years of hands-on experience in Silicon Design Verification.
- Expert-level proficiency in Verilog, System Verilog, and UVM coding.
- Strong experience with protocol verification and complex debugging scenarios.
- Familiarity with processor-based verification environments and SoC architectures.
- Proficiency with industry-standard simulation tools such as VCS, Xcelium, or Xsim.
- Experience with scripting languages like Python, Perl, or Makefile for verification automation.
- Solid understanding of digital logic design and computer architecture.
Education and Submission Requirements
- Bachelor’s, Master’s, or PhD in Computer Science, Electrical/Electronic Engineering, or a related field.
- Candidates MUST provide a valid LinkedIn profile link, a copy of their Visa, and a Driver’s License (DL) with their submission.
- Initial interviews will be conducted via Skype.
- Preference will be given to local candidates in the Santa Clara/Bay Area.
Join Adventa Tech and contribute to the development of next-generation silicon technology. We offer a dynamic work environment where innovation and technical mastery are at the forefront of our mission. This role provides the opportunity to work on cutting-edge protocols and methodologies in the heart of Silicon Valley.
Special Requirements
MUST HAVE LINKEDIN, VISA COPY, DL along with submissions. Mode of Interview: Skype. Need Local.
Compensation & Location
Salary: $175,000 – $245,000 per year (Estimated)
Location: Santa Clara, CA
Recruiter / Company – Contact Information
Recruiter / Employer: Adventa Tech Inc.
Email: jinatamana@adventatech.com
Recruiter Notice:
To remove this job posting, please send an email from
jinatamana@adventatech.com with the subject:
DELETE_JOB_ID_1284